Engineering Tech Brief: Better PCB Design using Stacked Vias

An effective Design Solution for Dense PCB Layout Challenges:

As modern electronic product form factors continue to shrink at the same time as physical component geometries become increasingly dense, the demands of routing complex components become progressively more difficult. This is often observed in designs incorporating high pin count FPGAs and fine pitch BGAs which require that fanouts be designed to access all of the device’s pins. In high density designs, the popular use of through-hole vias may consume too much space to be practical. For many of the current designs, effective PCB trace routing requires the use of a new design approach… these designs required the use of a stacked via.

The Stacked Via:

A stacked via consists of multiple vias layered directly on top of each other. Each via is first drilled and then metalized, leaving a small annular ring at the top and bottom to ensure electrical connection. This annular ring is typically very narrow – as thin as .002” – which means that registration must be extremely precise.

Because one via can be placed on top of another, stacked vias take up less space on a PCB than through-hole vias… and this makes successful routing of high density boards more practical and flexible. Good use of stacked vias allows full flexibility in layer connectivity. It also reduces the parasitic capacitance typically associated with via. Fabricating PCBs with stacked vias requires a greater number of steps in order to ensure a good inter-via connection is achieved.

However, even with slightly added costs, the greater flexibility in routing often makes the difference between successfully routing a design and an inability to do so… thus leading to better design solutions. The ACDi engineering team sees implementation of this layout technique becoming more practical and even required as component densities increase while board surface area continues to decrease.

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